When Intel surprise-launched the P4 3.2EE fourteen months ago, it was a strategic move that served the company well.  Even though the Athlon 64 FX-51 was still a strong competitor, the large L3 cache of the P4 3.2 EE gave that CPU a tremendous boost in many of the areas where the FX-51 utterly dominated the P4 3.2 (gaming was the principle culprit here).  Even if the FX-51 was still a stronger option, Intel now had their own enthusiast product line, with its own sky-high price, boosted performance, and bragging-rights capability. 

Since then, however, the gaming / enthusiast pendulum has swung ever-farther towards AMD.  When Intel launched the P4 3.2EE, it ran a full 45.45% faster than the FX-51.  The P4 3.4EE pushed this gap to a full 54.5% in February, FX-53 brought it back to 42% in March.  Since then, the two have stared at each other uneasily, with a few minor speed bumps on both sides. 

The launch of the Athlon 64 FX-55, however, shrunk the gap between the two chips to a mere 30%, and (in gaming), pummels the P4 EE heavily.  Today?s launch of the 3.46EE, however, should put an interesting new twist in P4 gaming performance.  The 60 MHz increase is irrelevant (a whopping 1.7% boost) but the new 1066 MHz bus is quite interesting indeed.

The Anatomy of the 3.46EE:  Why the Large L3?

One thing we want to cover before launching into testing is why the EE processor is designed the way it is.  The EE, in fact, is not a new design at all; it?s a re-badged Gallatin-core processor.  Gallatin is Intel?s XeonMP chip, designed for use primarily in 4-way servers and up. 

Because Intel?s server designs all share a single FSB, the memory controller must struggle to keep the demands of four chips fed, all with only a single desktop processor?s amount of bandwidth.  This can easily lead to stalls, delays, and wasted CPU cycles.  By loading each CPU with a large L3, Intel enables the processors to cache a substantial chunk of data they?d otherwise be requesting, thereby freeing the system bus.

In the single processor EE?s case, obviously there isn?t the same priority on freeing the system bus, but latency is still a key factor.  The key behind much of the Athlon 64?s high game performance is the on-die memory controller; while Intel cannot duplicate that in the EE, adding a large chunk of L3 cache still substantially improves the CPU latencies. 

Would a large L2 have been faster?  In theory, yes, but such a design would?ve required a re-spin of the core, along with substantially increased expenses.  L2 is more expensive than L3, just as L1 is more expensive than L2.  The performance increase in moving to an EE from a standard P4 is entirely dependent on the application; we?ve seen some tests skyrocket and others barely twitch. 

Cache, like everything else, functions under the law of diminishing marginal return.  Add another 128K of L2 to the Celeron, produce the Celly-D, and you see a huge performance jump.  Move from 256K on Willamette to 512K on Northwood, and performance jumps significantly again?but typically not quite as much as before.  Eventually, rising die costs and construction issues overpower the performance gain of adding cache, and it becomes economically undesirable. 

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• In Need of a Champion for Multiple Reasons (1 of 10)
• Corsair DDR2-667: Damned Impressive, by Any Measure: (2 of 10)
• Test Configuration, Notes (3 of 10)
• Synthetic Testing: (4 of 10)
• Office Performance: (5 of 10)
• MP3 and Video Encoding (6 of 10)
• 3D Rendering (7 of 10)
• Gaming (8 of 10)
• Performance Analysis (9 of 10)
• Conclusion: Stuck Between a Canterwood Rock and an AMD Hard Place. (10 of 10)